047004 - Memory Systems:
Fundamentals, Recent Research, Challenges, Opportunities

Room: 1003

Staff

  • Instructor: Onur Mutlu

    Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is also a faculty member at Carnegie Mellon University, where he previously held the William D. and Nancy W. Strecker Early Career Professorship.
    His current broader research interests are in computer architecture, systems, and bioinformatics.
    For more information, please see his webpage at https://people.inf.ethz.ch/omutlu/.


  • Teaching Assistant: Roman Kaplan

    Roman Kaplan is a PhD candidate at the faculty of Electrical Engineering at the Technion, working under the supervision of Prof. Ran Ginosar.
    His research interests are parallel computer architectures, in-data processing, and accelerator architectures for machine learning and bioinformatics.
    For more information, please see his webpage at romankap.github.io.


Announcements

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Course Material

Memory Systems Course Syllabus

Lecture Videos

Link to YouTube playlist

Lecture Slides

Lecture 1: (a) Memory Importance and Trends, (b) Course Logistics, (c) Main Memory and DRAM Basics (taught on Oct 8th)

Lecture 2: (a) Memory Scaling: Reliability & Security, (b) Flash Memory Reliability & Security, (c) DRAM Refresh (taught on Oct 9th)

Lecture 3: Processing-in-Memory (taught on Oct 9th)

Lecture 4: Low-Latency Memory (taught on Oct 10th)

Lecture 5: Emerging Memory Technologies (taught on Oct 10th)

Lecture 6: Memory Interference and QoS (taught on Oct 10th & 11th)

Lecture 7: Interconnects (taught on Oct 11th & 12th)

Lecture 8: Asymmetric Multi-Core

Papers for Review

Instructions

1) Kim et al., "Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors", in ISCA 2014
2) Ahn et al., "A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing", in ISCA 2015
3) Mutlu et al., "Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems", in ISCA 2008

Deadline: Monday, Oct 22nd. Saturday, Oct 27nd, end of day

Link to submission system
Please create an account before submitting (below the password field)

Additional Material

Background material from "Design of Digital Circuits" course at ETH:

Link to "Design of Digital Circuits" lecture video and slides

Materials from a similar course given by Onur at ACACES 2018:

Lecture slides from ACACES 2018
Lecture videos from ACACES 2018